ECED2200 - Digital Circuits - Course Syllabus

Marking Scheme

Labs	20 %
Assignments	10 %
Project	20 %
Final Exam	30 %
Lab Exam	20 %

Notes on Exams

Only non-programmable calculators are allowed. You will be provided with several sheets of reference material for the exam, no additional paper or references are allowed. You will be given this reference material at least two weeks before the final exam, however a new copy will be provided for you in the exam.

Course Contents

Planned Date	Actual Date Covered	Topic of Lectures	What’s Due Today	Bebop to the Boolean Boogie	Contemporary Logic Design
03-Jul	03-Jul	Introduction, Gates		Ch 6	Ch1, App B
04-Jul	03-Jul	Number Systems		Ch 7	App. A.
05-Jul	04-Jul	Binary Addition/Subtraction		Ch 8	App. A.
06-Jul	06-Jul	Lab #1

09-Jul	05-Jul	Boolean Algebra		Ch 9	Ch 2
10-Jul	09-Jul	Canonical Forms	Ass #1	Ch 9	Ch 2
11-Jul	10-Jul	Half/Full Adder Synthesis	Lab #1		Ch 2, Ch 5
12-Jul	12-Jul	Lab #2
13-Jul	13-Jul	Project Introduction

16-Jul	11-Jul	Pos/neg Logic, K-Maps		Ch 9/10	Ch 2
17-Jul	16-Jul	Gate Conversion, Delays, Oscillators, Hazards	Ass #2		Ch 3
18-Jul	17-Jul	Multiplexers & Decoders	Lab #2		Ch 4
19-Jul	19-Jul	Lab #3
20-Jul		NO CLASS		Ch 11	Ch 6

23-Jul	18-Jul	Sequential Logic		Ch 11	Ch 6
24-Jul	23-Jul	Shift Registers, Serial Protocols	Ass #3
25-Jul	25-Jul	Lab #4	Lab #3	Ch 11	Ch 6/7
26-Jul	26-Jul	Lab #5
27-Jul	23-Jul	Counters		Ch 11	Ch 7

30-Jul	24-Jul	Counters		Ch 11	Ch 7
31-Jul	30-Jul	Finite State Machines	Ass #4
01-Aug	31-Jul	Finite State Machines in VHDL	Lab #4	Ch 12	Ch 8
02-Aug		Lab #6	Lab #5	Ch 12	Ch 8
03-Aug		NO CLASS (I’ll be there so ask me questions)		Ch 12	Ch 8

07-Aug		Review/Request
08-Aug		Review/Request	Ass #5
09-Aug		Review/Request	Lab #6
10-Aug		Review/Request

13-Aug		Final Exam
14-Aug		Lab Test
15-Aug		Project Work
16-Aug		Project Work
17-Aug		Presentations	Proj. Report