Introduction to Digital Circuits (ECED2200)
Copyright Notice & Remixing this Course
All material for this course has been Creative Commons Attribution-ShareAlike 3.0 Unported License. If you need source files please ContactMe.
WARNING: If you are a student at Dalhousie University, be aware not all material on this page may be relevant. e.g. the Course Syllabus, Course Notes, Assignments, and Exam Info are ONLY valid when I’m the instructor. They will be WRONG if you are taking the regular course.
Textbook & Other Resources
The recommended text is “Bebop to the Boolean Boogie” by Clive Maxfield. This book is enjoyable to read (as far as digital logic books go) and will be an excellent reference. You can buy it from e.g.: Amazon.ca or Amazon.com, however at Dalhousie (and probably other universities) you have access to the electronic edition for free.
You may access it using the following link: Should work when ON university Campus. If you aren’t at a university yourself, you might be able to access this resource by using a computer in the library if they provide open access.
I have been told that the Kindle edition of this book has low-quality figures. You can try the Google Play version if you want an E-Book if your institution doesn’t provide access.
You may also find the following useful: Play-Hookey.com Asic-World Digital Logic Tutorial Fpga4Fun - Programmable logic intro
Course Notes
A version of the course notes is available: ECED2200 Course Notes
Hardware Required
The labs in this course use my Binary Explorer boards. You can see lots more tutorials and information linked form that site.
Some Useful Resources for the Hardware
Most Blocks available in Xilinx ISE for CPLD Additional Blocks you can use: TTL ones
Colin’s Lecture Material
| No | Topic | Slides | Videos | Other Material | |||
|---|---|---|---|---|---|---|---|
| 1 | Introduction, Gates, Number Systems | [digitalcircuits/Digital Circuits Slides 01 - Intro.pdf | Slides 1] | 1: Introduction & Gates2: Number Systems3: Summary | |||
| 2 | Adding/Subtracting in Binary, Signed Numbers | [digitalcircuits/Digital Circuits Slides 01 - Intro.pdf | Slides 1] | 1: Lecture2: Summary | |||
| 3 | Boolean Algebra | [digitalcircuits/Digital Circuits Slides 02 - Boolean Algebra.pdf | Slides 2] | 1: Lecture2: Summary | |||
| 4 | Canonical Forms | [digitalcircuits/Digital Circuits Slides 02 - Boolean Algebra.pdf | Slides 2] | 1: Lecture2: Summary | |||
| 5 | Adders & Subtractors | [digitalcircuits/Digital Circuits Slides 03 - AddersSubtractorsALU.pdf | Slides 3] | 1: Lecture2: Summary | |||
| 6 | Karnaugh Maps (K-Maps) | [digitalcircuits/Digital Circuits Slides 04 - K Maps.pdf | Slides 4] | 1: Lecture2: Summary | |||
| 7 | K-Maps with Equations, Gate Time Delay, Hazards | [digitalcircuits/Digital Circuits Slides 04 - K Maps.pdf | Slides 4] [digitalcircuits/Digital%20Circuits%20Slides%2005%20-%20Time%20Response%20Hazards.pdf | Slides 5] | 1: Lecture 2: Summary | ||
| 8 | Multiplexers and Demultiplexers | [digitalcircuits/Digital Circuits Slides 06 - Multiplex and Demultiplex.pdf | Slides 6] | 1: Lecture2: Summary | |||
| 9A | Programmable Logic | [digitalcircuits/Digital Circuits Slides 07 - Programmable Logic.pdf | Slides 7] | 1: Lecture | |||
| 9B | Sequential Logic #1 | [digitalcircuits/Digital Circuits Slides 08 - Sequential Logic.pdf | Slides 8] | 1: Lecture 2: Summary | |||
| 10A | Sequential Logic #2 | [digitalcircuits/Digital Circuits Slides 08 - Sequential Logic.pdf | Slides 8] | 2:Summary | |||
| 10B | Registers, Shift Registers, Serial Protocols | [digitalcircuits/Digital Circuits Slides 09 - Serial Protocols.pdf | Slides 9] | 2:Summary | |||
| 11 | Counters & Counter Design | [digitalcircuits/Digital Circuits Slides 10 - Counters.pdf | Slides 10] | 1:Lecture | |||
| 12 | Finite State Machine | [digitalcircuits/Digital Circuits Slides 11 - FSM.pdf | Slides 11] | 1:Lecture 2:Summary | |||
| 13 | HDL & VHDL | [digitalcircuits/Digital Circuits Slides 12 - VHDL.pdf | Slides 12] | 1:Lecture | [digitalcircuits/VHDL Example Mealy.pdf | MealyVHDL] [digitalcircuits/VHDL Example Moore.pdf | MooreVHDL] Project_Files |
| 14 | Course Review Part 1 | 1:Lecture | |||||
| 15 | Course Review Part 2 | 1:Lecture | |||||
| 16 | Course Review Part 3 | 1:Lecture |
Course Notes
Extensive course notes (>200 pages) are published for use with this course. Note they are not CC licensed and may not be reproduced. See: Download Course Notes
Labs
The lab report format is described in this document. Some labs only require a simple fill-in-the-blanks report which you can download from this website.
| Lab Number | Lab Name | Lab Instructions | Required Files | Videos | Intro Slides | |
|---|---|---|---|---|---|---|
| 1 | Basic Gates: Breadboard, Simulator, and Programmable | 1:Procedure | ||||
| 2:Hand In | 1:BORA Eraser | |||||
| 2:Example Project File | ||||||
| Part 1 | ||||||
| Part 2 | [digitalcircuits/Digital Circuits Lab Slides 01 - Breadboards and Gates.pdf | Slides] | ||||
| 2 | Arithmetic Elements | 1:Procedure | Lab 2 ISE Project (Digital Trainer Files) | Part 1 | [digitalcircuits/Digital Circuits Lab Slides 02 - Adders.pdf | Slides] |
| 3 | Encoders, Decoders, and Mux | 1:Procedure | ||||
| 2:Handout | Lab 3 ISE Project (Digital Trainer Files) | Part 1 | ||||
| 4 | Flip Flops, Registers | 1: Procedure 2:Observations Docx | Lab 4 ISE Project (Digital Trainer Files) | Part 1 | ||
| Part 2 | ||||||
| 5 | Shift Registers & Serial Protocols | 1: Procedure | ||||
| 3: Observations | Lab 5 ISE Project (Digital Trainer Files) | |||||
| 6 | Counters, Pulse Width Modulation | 1: Procedure | Lab 6 ISE Project (Digital Trainer Files) | |||
| 7 | No Lab 7 |
Specific Material & Due-Dates (possibly irrelevant)
The follwing material is only valid if you are taking a summer course taught by me.
Course Syllabus
Please download the 2013 Summer Course Syllabus to see expected lecture dates & due dates.
Assignments
You can work on the following assignments as you progress through the course material. Try not to look at the solutions until you’ve attempted the assignment or you’ll lose out on the value!
| Assignment Link | Due Date | Solutions |
|---|---|---|
| Assignment 1 | July 9,2013 | Solutions |
| Assignment 2 | July 16,2013 | Solutions |
| Assignment 3 | July 23,2013 | Solutions |
| Assignment 4 | July 30,2013 | Solutions |
| Assignment 5 | Aug 6,2013 | Solutions |
Final Exam
Reference Material for Exam (Cheat Sheet) Information on Exam Format & Coverage