Circuit-Cellar on Colin O'Flynn

Experimenting with Metastability and Multiple Clocks on FPGAs

Sat, 26 Dec 2020 22:58:43 +0000

NOTE: This article appeared in Issue 293 of Circuit Cellar, back in December 2014. I’ve posted it here for your reading pleasure as well. References to previous articles are for Circuit Cellar Issues, as this was originally written for the print publication. This version differs slightly from the print version – this is my own ‘author copy’ version before the Circuit Cellar editing. References to “ProgrammableLogicInPractice.com” are broken for now, but material has been mirrored to the bottom of this page.

FPGA Board Design Tips

Tue, 04 Aug 2020 16:33:34 +0000

NOTE: This article appeared in Issue 315 of Circuit Cellar, back in October 2016. I’ve posted it here for your reading pleasure as well. References to previous articles are for Circuit Cellar Issues, as this was originally written for the print publication. This version differs slightly from the print version - this is my own ‘author copy’ version before the Circuit Cellar editing.

Back in December 2015, I discussed how I solder BGA devices (such as FPGAs) using a low-cost reflow oven. This article will discuss the design of the FPGA board itself, which you could then assemble using the tips in my previous article.

Programmable Logic in Practice

Thu, 19 Sep 2013 00:39:00 +0000

I wrote for Circuit Cellar in a column titled “Programmable Logic in Practice” from 2013-2015. This column detailed various work around FPGAs. The column later became my “Embedded System Essentials” column, which primarily dealt with security issues in embedded systems.

The previous domain (programmablelogicinpractice.com) now redirects here. Unfortunately not all posts were transitioned. You can find copies of some of my articles if you check the Circuit Cellar tag.

Circuit Cellar 25th Anniversary Edition

Sat, 06 Apr 2013 04:48:00 +0000

I’ve got an article in the 25th-Anniversary edition of Circuit Cellar about the future of FPGAs. If you haven’t got an issue yourself yet, check out their webstore.

Design a FIR Filter in an FPGA in 30 mins using High Level Synthesis

Sat, 26 Jan 2013 18:25:00 +0000

I’ve been working with Xilinx’s new High Level Synthesis tools built into Vivado. I’m slowly working on posting some more complete tutorials. In the mean-time here is a simple tutorial about making a Finite Impulse Response Filter on a real ADC/DAC board .