[COREGEN.VERILOG Component Instantiation.division_core]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="division_core YourInstanceName ("
text007="    .dividend(dividend),"
text008="    .divisor(divisor),"
text009="    .quot(quot),"
text010="    .remd(remd),"
text011="    .c(c));"
text012=""
text013=" "
type=template
[COREGEN.VERILOG Component Instantiation.freqtable_ram]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="freqtable_ram YourInstanceName ("
text007="    .A(A),"
text008="    .CLK(CLK),"
text009="    .D(D),"
text010="    .WE(WE),"
text011="    .SPO(SPO));"
text012=""
text013=" "
type=template
[COREGEN.VERILOG Component Instantiation.freqtable_ramcomp]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="freqtable_ramcomp YourInstanceName ("
text007="    .addr(addr),"
text008="    .clk(clk),"
text009="    .din(din),"
text010="    .dout(dout),"
text011="    .we(we));"
text012=""
text013=" "
type=template
[COREGEN.VERILOG Component Instantiation.image]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="image YourInstanceName ("
text007="    .addr(addr),"
text008="    .clk(clk),"
text009="    .din(din),"
text010="    .dout(dout),"
text011="    .we(we));"
text012=""
text013=" "
type=template
[COREGEN.VERILOG Component Instantiation.line_buffer]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="line_buffer YourInstanceName ("
text007="    .CLK(CLK),"
text008="    .D(D),"
text009="    .Q(Q),"
text010="    .CE(CE));"
text011=""
text012=" "
type=template
[COREGEN.VERILOG Component Instantiation.quad_count]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="quad_count YourInstanceName ("
text007="    .addr(addr),"
text008="    .clk(clk),"
text009="    .din(din),"
text010="    .dout(dout),"
text011="    .we(we));"
text012=""
text013=" "
type=template
[COREGEN.VHDL Component Instantiation.division_core]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component division_core"
text005="    port ("
text006="    dividend: IN std_logic_VECTOR(9 downto 0);"
text007="    divisor: IN std_logic_VECTOR(9 downto 0);"
text008="    quot: OUT std_logic_VECTOR(9 downto 0);"
text009="    remd: OUT std_logic_VECTOR(7 downto 0);"
text010="    c: IN std_logic);"
text011="end component;"
text012=""
text013=""
text014=""
text015=" "
text016="-------------------------------------------------------------"
text017=" "
text018="-- The following code must appear in the VHDL architecture body."
text019="-- Substitute your own instance name and net names."
text020=" "
text021="your_instance_name : division_core"
text022="        port map ("
text023="            dividend => dividend,"
text024="            divisor => divisor,"
text025="            quot => quot,"
text026="            remd => remd,"
text027="            c => c);"
text028=" "
type=template
[COREGEN.VHDL Component Instantiation.freqtable_ram]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component freqtable_ram"
text005="    port ("
text006="    A: IN std_logic_VECTOR(7 downto 0);"
text007="    CLK: IN std_logic;"
text008="    D: IN std_logic_VECTOR(11 downto 0);"
text009="    WE: IN std_logic;"
text010="    SPO: OUT std_logic_VECTOR(11 downto 0));"
text011="end component;"
text012=""
text013=""
text014=""
text015=" "
text016="-------------------------------------------------------------"
text017=" "
text018="-- The following code must appear in the VHDL architecture body."
text019="-- Substitute your own instance name and net names."
text020=" "
text021="your_instance_name : freqtable_ram"
text022="        port map ("
text023="            A => A,"
text024="            CLK => CLK,"
text025="            D => D,"
text026="            WE => WE,"
text027="            SPO => SPO);"
text028=" "
type=template
[COREGEN.VHDL Component Instantiation.freqtable_ramcomp]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component freqtable_ramcomp"
text005="    port ("
text006="    addr: IN std_logic_VECTOR(7 downto 0);"
text007="    clk: IN std_logic;"
text008="    din: IN std_logic_VECTOR(11 downto 0);"
text009="    dout: OUT std_logic_VECTOR(11 downto 0);"
text010="    we: IN std_logic);"
text011="end component;"
text012=""
text013=""
text014=""
text015=" "
text016="-------------------------------------------------------------"
text017=" "
text018="-- The following code must appear in the VHDL architecture body."
text019="-- Substitute your own instance name and net names."
text020=" "
text021="your_instance_name : freqtable_ramcomp"
text022="        port map ("
text023="            addr => addr,"
text024="            clk => clk,"
text025="            din => din,"
text026="            dout => dout,"
text027="            we => we);"
text028=" "
type=template
[COREGEN.VHDL Component Instantiation.image]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component image"
text005="    port ("
text006="    addr: IN std_logic_VECTOR(7 downto 0);"
text007="    clk: IN std_logic;"
text008="    din: IN std_logic_VECTOR(11 downto 0);"
text009="    dout: OUT std_logic_VECTOR(11 downto 0);"
text010="    we: IN std_logic);"
text011="end component;"
text012=""
text013=""
text014=""
text015=" "
text016="-------------------------------------------------------------"
text017=" "
text018="-- The following code must appear in the VHDL architecture body."
text019="-- Substitute your own instance name and net names."
text020=" "
text021="your_instance_name : image"
text022="        port map ("
text023="            addr => addr,"
text024="            clk => clk,"
text025="            din => din,"
text026="            dout => dout,"
text027="            we => we);"
text028=" "
type=template
[COREGEN.VHDL Component Instantiation.line_buffer]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component line_buffer"
text005="    port ("
text006="    CLK: IN std_logic;"
text007="    D: IN std_logic_VECTOR(7 downto 0);"
text008="    Q: OUT std_logic_VECTOR(7 downto 0);"
text009="    CE: IN std_logic);"
text010="end component;"
text011=""
text012=""
text013=""
text014=" "
text015="-------------------------------------------------------------"
text016=" "
text017="-- The following code must appear in the VHDL architecture body."
text018="-- Substitute your own instance name and net names."
text019=" "
text020="your_instance_name : line_buffer"
text021="        port map ("
text022="            CLK => CLK,"
text023="            D => D,"
text024="            Q => Q,"
text025="            CE => CE);"
text026=" "
type=template
[COREGEN.VHDL Component Instantiation.quad_count]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component quad_count"
text005="    port ("
text006="    addr: IN std_logic_VECTOR(0 downto 0);"
text007="    clk: IN std_logic;"
text008="    din: IN std_logic_VECTOR(9 downto 0);"
text009="    dout: OUT std_logic_VECTOR(9 downto 0);"
text010="    we: IN std_logic);"
text011="end component;"
text012=""
text013=""
text014=""
text015=" "
text016="-------------------------------------------------------------"
text017=" "
text018="-- The following code must appear in the VHDL architecture body."
text019="-- Substitute your own instance name and net names."
text020=" "
text021="your_instance_name : quad_count"
text022="        port map ("
text023="            addr => addr,"
text024="            clk => clk,"
text025="            din => din,"
text026="            dout => dout,"
text027="            we => we);"
text028=" "
type=template
