--------------------------------------------------------------------------------
--     This file is owned and controlled by Xilinx and must be used           --
--     solely for design, simulation, implementation and creation of          --
--     design files limited to Xilinx devices or technologies. Use            --
--     with non-Xilinx devices or technologies is expressly prohibited        --
--     and immediately terminates your license.                               --
--                                                                            --
--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
--     FOR A PARTICULAR PURPOSE.                                              --
--                                                                            --
--     Xilinx products are not intended for use in life support               --
--     appliances, devices, or systems. Use in such applications are          --
--     expressly prohibited.                                                  --
--                                                                            --
--     (c) Copyright 1995-2003 Xilinx, Inc.                                   --
--     All rights reserved.                                                   --
--------------------------------------------------------------------------------
-- You must compile the wrapper file division_core.vhd when simulating
-- the core, division_core. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Guide".

-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

-- synopsys translate_off
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

Library XilinxCoreLib;
ENTITY division_core IS
	port (
	dividend: IN std_logic_VECTOR(9 downto 0);
	divisor: IN std_logic_VECTOR(9 downto 0);
	quot: OUT std_logic_VECTOR(9 downto 0);
	remd: OUT std_logic_VECTOR(7 downto 0);
	c: IN std_logic);
END division_core;

ARCHITECTURE division_core_a OF division_core IS

component wrapped_division_core
	port (
	dividend: IN std_logic_VECTOR(9 downto 0);
	divisor: IN std_logic_VECTOR(9 downto 0);
	quot: OUT std_logic_VECTOR(9 downto 0);
	remd: OUT std_logic_VECTOR(7 downto 0);
	c: IN std_logic);
end component;

-- Configuration specification 
	for all : wrapped_division_core use entity XilinxCoreLib.dividervht(behavioral)
		generic map(
			dividend_width => 10,
			signed_b => 0,
			fractional_b => 1,
			divisor_width => 10,
			fractional_width => 8,
			divclk_sel => 1);
BEGIN

U0 : wrapped_division_core
		port map (
			dividend => dividend,
			divisor => divisor,
			quot => quot,
			remd => remd,
			c => c);
END division_core_a;

-- synopsys translate_on

