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--     solely for design, simulation, implementation and creation of          --
--     design files limited to Xilinx devices or technologies. Use            --
--     with non-Xilinx devices or technologies is expressly prohibited        --
--     and immediately terminates your license.                               --
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--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
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--     (c) Copyright 1995-2003 Xilinx, Inc.                                   --
--     All rights reserved.                                                   --
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-- You must compile the wrapper file line_buffer.vhd when simulating
-- the core, line_buffer. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Guide".

-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

-- synopsys translate_off
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

Library XilinxCoreLib;
ENTITY line_buffer IS
	port (
	CLK: IN std_logic;
	D: IN std_logic_VECTOR(7 downto 0);
	Q: OUT std_logic_VECTOR(7 downto 0);
	CE: IN std_logic);
END line_buffer;

ARCHITECTURE line_buffer_a OF line_buffer IS

component wrapped_line_buffer
	port (
	CLK: IN std_logic;
	D: IN std_logic_VECTOR(7 downto 0);
	Q: OUT std_logic_VECTOR(7 downto 0);
	CE: IN std_logic);
end component;

-- Configuration specification 
	for all : wrapped_line_buffer use entity XilinxCoreLib.C_SHIFT_RAM_V6_0(behavioral)
		generic map(
			c_has_aset => 0,
			c_read_mif => 0,
			c_has_a => 0,
			c_sync_priority => 1,
			c_has_sclr => 0,
			c_width => 8,
			c_enable_rlocs => 1,
			c_default_data_radix => 1,
			c_generate_mif => 1,
			c_ainit_val => "00000000",
			c_has_ce => 1,
			c_has_aclr => 0,
			c_mem_init_radix => 1,
			c_sync_enable => 0,
			c_depth => 800,
			c_has_ainit => 0,
			c_sinit_val => "00000000",
			c_has_sset => 0,
			c_has_sinit => 0,
			c_shift_type => 0,
			c_mem_init_file => "line_buffer.mif",
			c_default_data => "0",
			c_reg_last_bit => 0,
			c_addr_width => 10);
BEGIN

U0 : wrapped_line_buffer
		port map (
			CLK => CLK,
			D => D,
			Q => Q,
			CE => CE);
END line_buffer_a;

-- synopsys translate_on

