
-- VHDL Test Bench Created from source file frequency_table.vhd -- 10:08:21 03/16/2004
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all;
use work.classio.all;

ENTITY frequency_table_core_freq_table_counter_testbench_vhd_tb IS
END frequency_table_core_freq_table_counter_testbench_vhd_tb;

ARCHITECTURE behavior OF frequency_table_core_freq_table_counter_testbench_vhd_tb IS 

	COMPONENT frequency_table
	PORT(
		reset_in : IN std_logic;
		dataclk_in : IN std_logic;
		dbldataclk_in : IN std_logic;
    		dataclk90_in		: in std_logic;
		data_in : IN std_logic_vector(7 downto 0);
		data_rdy_in : IN std_logic;
		record_in : IN std_logic;
		lowerlimit_in : IN std_logic_vector(7 downto 0);
		upperlimit_in : IN std_logic_vector(7 downto 0);
		sort_addr_in : IN std_logic_vector(2 downto 0);          
		reset_out : OUT std_logic;
		data_rdy_out : OUT std_logic;
		data_out : OUT std_logic_vector(7 downto 0);
		datacount_out : OUT std_logic_vector(11 downto 0)
		);
	END COMPONENT;

	SIGNAL reset_in :  std_logic;
	SIGNAL reset_out :  std_logic;
	SIGNAL dataclk_in :  std_logic;
	SIGNAL dbldataclk_in :  std_logic;
	SIGNAL dataclk90_in		: std_logic;
	SIGNAL data_in :  std_logic_vector(7 downto 0);
	SIGNAL data_rdy_in :  std_logic;
	SIGNAL record_in :  std_logic;
	SIGNAL lowerlimit_in :  std_logic_vector(7 downto 0);
	SIGNAL upperlimit_in :  std_logic_vector(7 downto 0);
	SIGNAL data_rdy_out :  std_logic;
	SIGNAL sort_addr_in :  std_logic_vector(2 downto 0);
	SIGNAL data_out :  std_logic_vector(7 downto 0);
	SIGNAL datacount_out :  std_logic_vector(11 downto 0);

BEGIN

	uut: frequency_table PORT MAP(
		reset_in => reset_in,
		reset_out => reset_out,
		dataclk_in => dataclk_in,
		dataclk90_in => dataclk90_in,
		dbldataclk_in => dbldataclk_in,
		data_in => data_in,
		data_rdy_in => data_rdy_in,
		record_in => record_in,
		lowerlimit_in => lowerlimit_in,
		upperlimit_in => upperlimit_in,
		data_rdy_out => data_rdy_out,
		sort_addr_in => sort_addr_in,
		data_out => data_out,
		datacount_out => datacount_out
	);


-- *** Test Bench - User Defined Section ***

 
   clk: process
   begin
   if dataclk_in = '0' then
   	dataclk_in <= '1';
   else
   	dataclk_in <= '0';
   end if;
   wait for 20 ns;
   end process;
   
   dblkclk: process
   begin
   if dbldataclk_in = '0' then
   	dbldataclk_in <= '1';
   else
   	dbldataclk_in <= '0';
   end if;
   wait for 10 ns;
   end process;
   
   clk90: process
   begin
   if dataclk90_in = 'U' then
   	wait for 15 ns;
   	dataclk90_in <= '0';
   elsif dataclk90_in = '0' then
   	dataclk90_in <= '1';
 	   wait for 20 ns;
   else
   	dataclk90_in <= '0';
 	wait for 20 ns;
   end if;
   end process;	
   

   main: process
   
   file infile:TEXT open read_mode is "freq_count_test_vectors.in";
   file outfile:TEXT open write_mode is "freq_count_test_vectors.out";
   variable buf: line;
   variable input_colour: std_logic_vector(7 downto 0);
   
   begin
   
   --reset the main system, which will clear all the ram
   reset_in <= '0';
   wait for 20 ns;
   reset_in <= '1';
   wait until reset_out = '1';
   wait for 20 ns;
   reset_in <= '0';
   
   --start recording
   record_in <= '1';
   

   --read in all the test vectors
   while not (endfile (infile)) loop
	wait until falling_edge(dataclk_in);
	read_v1d (infile, input_colour);
	data_in <= input_colour;
   end loop;
   
   --wait a bit
   wait for 20 ns;
   
   record_in <= '0';
   
   --wait till we are finished recording
   wait until data_rdy_out = '1';
   
   wait for 20 ns;
   
   sort_addr_in <= "000";
   wait for 10 ns;
   write_v1d(outfile, data_out);
   write_v1d(outfile, datacount_out);
     
   sort_addr_in <= "001";
   wait for 10 ns;
   write_v1d(outfile, data_out);
   write_v1d(outfile, datacount_out);
   
   sort_addr_in <= "010";
   wait for 10 ns;
   write_v1d(outfile, data_out);
   write_v1d(outfile, datacount_out);
   
   sort_addr_in <= "011";
   wait for 10 ns;
   write_v1d(outfile, data_out);
   write_v1d(outfile, datacount_out);
   
   sort_addr_in <= "100";
   wait for 10 ns;
   write_v1d(outfile, data_out);
   write_v1d(outfile, datacount_out);
   
   sort_addr_in <= "101";
   wait for 10 ns;
   write_v1d(outfile, data_out);
   write_v1d(outfile, datacount_out);
   
    sort_addr_in <= "110";
   wait for 10 ns;
   write_v1d(outfile, data_out);
   write_v1d(outfile, datacount_out);
  
     sort_addr_in <= "111";
   wait for 10 ns;
   write_v1d(outfile, data_out);
   write_v1d(outfile, datacount_out);
  
   --done
   wait;
   end process;

   tb : PROCESS
   BEGIN
   	lowerlimit_in <= "00000001";
   	upperlimit_in <= "11111110";
   
   	data_rdy_in <= '1';
   	
         wait; -- will wait forever
   END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;
