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// The synopsys directives "translate_off/translate_on" specified
// below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
// synthesis tools. Ensure they are correct for your synthesis tool(s).

// You must compile the wrapper file division_core.v when simulating
// the core, division_core. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Guide".

module division_core (
	dividend,
	divisor,
	quot,
	remd,
	c);    // synthesis black_box

input [9 : 0] dividend;
input [9 : 0] divisor;
output [9 : 0] quot;
output [7 : 0] remd;
input c;

// synopsys translate_off

	DIVIDERVHT #(
		1,	// divclk_sel
		10,	// dividend_width
		10,	// divisor_width
		1,	// fractional_b
		8,	// fractional_width
		0)	// signed_b
	inst (
		.DIVIDEND(dividend),
		.DIVISOR(divisor),
		.QUOT(quot),
		.REMD(remd),
		.C(c));


// synopsys translate_on

// FPGA Express black box declaration
// synopsys attribute fpga_dont_touch "true"
// synthesis attribute fpga_dont_touch of division_core is "true"

// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of division_core is "black_box"

endmodule

