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// The synopsys directives "translate_off/translate_on" specified
// below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
// synthesis tools. Ensure they are correct for your synthesis tool(s).

// You must compile the wrapper file line_buffer.v when simulating
// the core, line_buffer. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Guide".

module line_buffer (
	CLK,
	D,
	Q,
	CE);    // synthesis black_box

input CLK;
input [7 : 0] D;
output [7 : 0] Q;
input CE;

// synopsys translate_off

	C_SHIFT_RAM_V6_0 #(
		10,	// c_addr_width
		"00000000",	// c_ainit_val
		"0",	// c_default_data
		1,	// c_default_data_radix
		800,	// c_depth
		1,	// c_enable_rlocs
		1,	// c_generate_mif
		0,	// c_has_a
		0,	// c_has_aclr
		0,	// c_has_ainit
		0,	// c_has_aset
		1,	// c_has_ce
		0,	// c_has_sclr
		0,	// c_has_sinit
		0,	// c_has_sset
		"line_buffer.mif",	// c_mem_init_file
		1,	// c_mem_init_radix
		0,	// c_read_mif
		0,	// c_reg_last_bit
		0,	// c_shift_type
		"00000000",	// c_sinit_val
		0,	// c_sync_enable
		1,	// c_sync_priority
		8)	// c_width
	inst (
		.CLK(CLK),
		.D(D),
		.Q(Q),
		.CE(CE),
		.A(),
		.SCLR(),
		.SINIT(),
		.SSET(),
		.ACLR(),
		.AINIT(),
		.ASET());


// synopsys translate_on

// FPGA Express black box declaration
// synopsys attribute fpga_dont_touch "true"
// synthesis attribute fpga_dont_touch of line_buffer is "true"

// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of line_buffer is "black_box"

endmodule

