Fpga on Colin O'Flynn

Experimenting with Metastability and Multiple Clocks on FPGAs

Sat, 26 Dec 2020 22:58:43 +0000

NOTE: This article appeared in Issue 293 of Circuit Cellar, back in December 2014. I’ve posted it here for your reading pleasure as well. References to previous articles are for Circuit Cellar Issues, as this was originally written for the print publication. This version differs slightly from the print version – this is my own ‘author copy’ version before the Circuit Cellar editing. References to “ProgrammableLogicInPractice.com” are broken for now, but material has been mirrored to the bottom of this page.

FPGA Board Design Tips

Tue, 04 Aug 2020 16:33:34 +0000

NOTE: This article appeared in Issue 315 of Circuit Cellar, back in October 2016. I’ve posted it here for your reading pleasure as well. References to previous articles are for Circuit Cellar Issues, as this was originally written for the print publication. This version differs slightly from the print version - this is my own ‘author copy’ version before the Circuit Cellar editing.

Back in December 2015, I discussed how I solder BGA devices (such as FPGAs) using a low-cost reflow oven. This article will discuss the design of the FPGA board itself, which you could then assemble using the tips in my previous article.

Side-Channel Power Analysis of AES Core in Project Vault

Sun, 31 May 2015 17:13:37 +0000

What is Project Vault

You can read a quick overview on various news sites, but basically project vault gives you a cryptographic module that you have complete control over. This means *you* decide to trust the module - even to the point of being able to access to implementation details of the crypto cores. Basically Project Vault is a solution to how you can avoid having unknown backdoors in your hardware. Rather than having to trust some vendor of security modules, you can make sure things are done correctly.

Programmable Logic in Practice

Thu, 19 Sep 2013 00:39:00 +0000

I wrote for Circuit Cellar in a column titled “Programmable Logic in Practice” from 2013-2015. This column detailed various work around FPGAs. The column later became my “Embedded System Essentials” column, which primarily dealt with security issues in embedded systems.

The previous domain (programmablelogicinpractice.com) now redirects here. Unfortunately not all posts were transitioned. You can find copies of some of my articles if you check the Circuit Cellar tag.

Split Ground Plane: Example of failing high-speed signals

Sat, 06 Apr 2013 01:16:00 +0000

I’ve got a SASEBO-W board, which has a FPGA & a FT2232H for high-speed USB comms. I was seeing errors on the high-speed USB device, and couldn’t figure out why:

Power Split

The SASEBO-W is a multi-purpose board including a Xilinx LX150 Spartan 6 FPGA and a FTDI FT2232H USB interface. One use of the board is for measuring the power consumption of the FPGA and using that power consumption to perform power analysis attacks. I believe for this reason the ground planes are split, to facilitate making those measurements. This split plane is joined through a common-mode choke. To use the high-speed USB interface it requires passing signals across a split in the plane – something very undesirable. The following figure shows what the ground currents for these signals would be. The signals are running on a 60 MHz clock if using the fastest available FT2232H mode. A measurement of the potential difference between the two planes (done at CN3) shows the following figure. This is due to the 60 MHz clock being driven from the FT2232H to the FPGA, there was no data being transferred in this image. Note that the FPGA I/O interface is 2.5V, meaning that signals being sent from the FPGA to the FT2232H will already have a reduced amplitude compared to the 3.3V I/O voltage. There should be enough headroom in practice such this interface works OK, and the FPGA has 3.3V tolerant I/Os. The following figure shows a data bus line measured at the FT2232H in blue, the horizontal markers are set at 2.0V and 0.8V respectively, which are the limits for logic High/Low at the FT2232H. Note that due to this ground noise the signal is degraded to the point of crossing this threshold! If we mount a jumper on CN3 this shorts the two ground planes together. This isn’t an ideal low-impedance path, but it will make an improvement. In the above figure the yellow line is with this jumper mounted. The following figure shows the voltage difference between the two planes with such a jumper mounted. Compare to the earlier figure where the peak-to-peak voltage was almost 500mV! Monitoring both the ground difference and bus lines show when the line switch there is still some extra noise contributed – the green line below (NB: note scale differs from above figure) shows a still fair amount of bounce during the transition, but in practice the USB communication seems reliable between the FT2232H and the FPGA. So, that’s why you cannot cross high-speed traces across split planes!

Design a FIR Filter in an FPGA in 30 mins using High Level Synthesis

Sat, 26 Jan 2013 18:25:00 +0000

I’ve been working with Xilinx’s new High Level Synthesis tools built into Vivado. I’m slowly working on posting some more complete tutorials. In the mean-time here is a simple tutorial about making a Finite Impulse Response Filter on a real ADC/DAC board .

High-Speed ADC with Variable Gain Amp Input

Mon, 04 Jun 2012 01:15:00 +0000

Here is an ongoing project: it’s a high-speed ADC combined with some nice input preprocessing (amplifier). It’s all controlled by a FPGA on the Avnet LX9 Microboard, so it just plugs into that. Here is a simple python app (still being improved) to control it: Still need to measure analog BW to see how my layout stood out…

Avnet Spartan-6 LX9 Board: Or How ChipScope is your Saviour

Sat, 11 Feb 2012 15:24:00 +0000

I was recently working on a project which needed more gates than I had in my trusty current FPGA Board (Spartan3-200 on DLP-FPGA-HS). I quickly found the Avnet Spartan 6 LX9 board (AES-S6MB-LX9-G), which I could buy for $90 and have here in a few days. It also comes with a license for SDK for ChipScope, as it’s designed for experimenting with on-FPGA processors. It doesn’t have a full EDK license so you are a little limited in peripherals… But for my project I didn’t care about that. I was however interested in ChipScope Pro, having used it previously at a job. This quick post will show you how valuable it can be - the license included with the LX9 board is “device locked” and will only work with XA6SLX9 parts. ChipScope Pro is not normally licensed as part of WebPack so the $90 board is a great deal when you consider the licensing cost. My normal FPGA debugging, beyond Verilog testbenching, is to use a LogicPort on some spare IO lines. This works well - the LogicPort has a very high sampling rate (200MHz external, 500MHz internal). But it requires a physical connection, which requires a lot of IO pins. I was hoping ChipScope could eliminate this problem. There is two cores of interest: the Integrated Logic Analyser (ILA) core, and the Virtual IO (VIO) core. They are both controlled by the Integrated Controller (ICON) core. You can only have one ICON, but it can control up to a number of ILA/VIO cores. The VIO core gives you a virtual dashboard, where you can toggle bits and see results. This is pretty handy for validating/playing with cores to check they function as intended. Here I am checking a UART core from fpga4fun.com: Note the VIO core doesn’t provide buffering, so data is transferred over the JTAG. This limits your polling speed of course, but makes it easy to play with things. It does let you define pulse trains or single pulses if you have special timing requirements on e.g.: load lines, as I had here. The ILA core is strictly input. But it connects to BRAMs on-board the device, meaning you can buffer a fair amount of data. Since it’s all on-device the speed is basically limited by similar constraints to the rest of your design. Of course if you already have a packed chip you might not be able to spare any BRAMs… Here I am debugging a state machine, note you how can even define ’tokens’ so it decodes the states correctly: So the combination of ChipScope ILA + VIO I’m hoping will make designs go by a lot faster.